1. Field of the Invention
The present invention relates to a semiconductor device such as a semiconductor memory device or the like and a manufacturing method thereof, and more particularly, to an MIS (Metal Insulator Semiconductor) type semiconductor device in which a silicide layer is formed on a gate electrode and source/drain regions, and a manufacturing method thereof.
2. Description of the Background Art
FIG. 35 is a cross section showing a conventional semiconductor device disclosed, for example, in Japanese Patent Laying-Open No. 2-54536. As shown in FIG. 35, a number of active regions are separated from each other by an element isolation region 2 formed of a field insulating film at a surface of a semiconductor substrate 1 made of p-type monocrystalline silicon, and an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed therein.
The MOSFET has a gate electrode 5 located on a thin gate insulating layer 3 formed of silicon dioxide, and source/drain regions 6 formed at the surface of semiconductor substrate 1.
Gate electrode 5 is constituted by a silicon layer 4 on which low-resistance silicide layers 8a and 8b are formed, and a low-resistance silicide layer 8c is formed on each of source/drain regions 6. The total thickness of silicide layers 8a and 8b on silicon layer 4 is larger than a thickness of silicide layer 8c formed on each of source/drain regions 6.
Sidewalls 9 made of insulating material such as silicon oxide film or the like are formed on side portions of gate insulating layer 3, silicon layer 4, and silicide layers 8a and 8b by CVD (Chemical Vapor Deposition) technique and reactive etching.
In addition, an insulating film 10 and an interconnection layer 11 are formed on the elements formed as described above. A top surface of insulating film 10 has a difference in level corresponding to that of a lower layer. A portion of interconnection layer 11 is in contact with silicide layer 8c on source/drain region 6 through a contact 12. Furthermore, an n.sup.+ diffusion region 7a having high impurity concentration is formed under source/drain regions 6, and an n.sup.- diffusion region 7b having low impurity concentration is formed under sidewall 9.
The reason why the total thickness of silicide layers 8a and 8b on gate electrode 5 is made larger than a thickness of silicide layer 8c on source/drain region 6 in the conventional semiconductor device is that formation of a thicker silicide layer enables reduction in sheet resistance.
Since the conventional semiconductor device is constituted in such a manner as described above, sheet resistance of gate electrode 5 has been reduced, and source/drain regions 6 have been prevented from being etched through at the time of forming a contact hole. Recently, however, we found that technique of planarizing a formed layer in formation of a semiconductor device, that is, a CMP (Chemical Mechanical Polishing) method which was hardly used at home as of August, 1988 when patent application on this conventional semiconductor device was filed, has been used, causing the following problems.
FIG. 36 is a cross section showing a semiconductor device formed by means of a conventional technique, in which an insulating layer 10 is formed at least on a silicon layer 4 and source/drain regions 6 by a technique such as CVD to have a uniform thickness. A contact hole 12a is formed to be in contact with a silicide layer 8 on a gate electrode 5. A contact hole 12b is formed to be in contact with a silicide layer 8 on source/drain region 6. Silicide layer 8 on gate electrode 5 and silicide layer 8 on each source/drain region 6 have the same thickness. The same reference as that shown in FIG. 35 indicates the same or a corresponding portion.
As shown in FIG. 36, a thickness A of insulating layer 10 on silicide layer 8 formed on an element isolation region 2 and a thickness B of insulating layer 10 on source/drain region 6 formed at a main surface of a semiconductor substrate 1 are approximately the same. In addition, a surface 10a of insulating layer 10 has a difference in level C as shown in the figure. If surface 10a of insulating layer 10 is uneven as described above, problems such as degradation in accuracy of the dimension in forming an interconnection and an element, disconnection of the interconnection or the like occur.
Top surface 10a of insulating layer 10 is planarized as shown in FIG. 37 when processed by means of the above described CMP method, the difference in level C of top surface 10a of insulating layer 10 shown in FIG. 36 is eliminated, and a thickness D of insulating layer 10 on silicide layer 8 formed on element isolation region 2, that is, a depth D of contact hole 12a to be formed is significantly reduced compared to that of insulating layer 10 which has not been planarized.
On the other hand, a thickness E of insulating layer 10 on source/drain region 6, that is, a depth E of contact hole 12b to be formed can be made approximately the same as that of insulating layer 10 which has not been planarized.
It is noted that silicide layer 8 on gate electrode 5 and silicide layer 8 on each source/drain region 6 has the same thickness.
We found that, in the case of forming planarized insulating layer 10 and forming a contact simultaneously on both source/drain region 6 and gate electrode 5, if insulating layer 10 is etched to form complete contact hole 12b which is in contact with source/drain region 6, gate electrode 5 is etched through because insulating layer 10 on gate electrode 5 is thinner than that on source/drain region 6, causing malfunction of a semiconductor device.
We also found that, in the conventional example shown in FIG. 37, although silicide layer 8 is formed on gate electrode 5 and the like, use of insulating layer 10 planarized by the CMP method makes it more difficult to prevent an electrode from being etched through in formation of a contact hole than in the conventional example.